1. Field of the Invention
The present invention relates to logic synthesis of a logic circuit or ASIC.
2. State of the Art
Logic synthesis tools are used to interpret a description of a hardware circuit or logic ASIC so as to generate a final optimized silicon implementation of the circuit or system. Currently, most logic hardware (e.g., in ASIC form) is modeled and simulated by a designer writing an RTL (register-transfer level) description which corresponds to the function to be performed by the hardware or system. A RTL description is a hardware description language (HDL) description which describes the ASIC in terms of structural elements such as AND, NAND, or NOR gates. These gates are either explicitly called out or implicitly inferred by a boolean equation. The RTL description may also specify sequential elements such as latches and flip flops. There may also be a finite state machine description specifying a state transition graph. The following is an example of an RTL description: